Nonvolatile memory device and method for fabricating the same

ABSTRACT

A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2010-0051427, filed on May 31, 2010, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to a nonvolatilememory device, and more particularly, to a nonvolatile memory device anda method for fabricating the same.

In a three-dimensional nonvolatile memory device, a U-shaped stringstructure is a structure in which a source selection gate and a drainselection gate are formed over a memory string. It is known that theU-shaped string structure is very advantageous in view of devicecharacteristics, as compared with a vertical string structure in whichselection gates are formed above and under a memory string. To operatethe U-shaped memory string, a transistor for electrical coupling isrequired at the bottom. Such a transistor is called a pipe channeltransistor.

Two strings coupled to a source and a drain are coupled by a pipechannel transistor. In addition, control gate electrodes of two stringsmust be separated from each other by an etching process.

FIG. 1 is a cross-sectional view of a conventional nonvolatile memorydevice.

Referring to FIG. 1, a pipe gate 12 is formed on a bottom substrate 11.A first string MS1 and a second string MS2 are formed on the pipe gate12. The first string MS1 and the second pipe string MS2 are coupledtogether by a pipe channel 17A to thereby constitute a single memorystring.

The first string MS1 and the second string MS2 include a cell stack inwhich first insulation layers 13 and control gate electrodes 14 arealternately stacked several times. The cell stack and the pipe gate 12are etched to form a cell channel hole 15 and a pipe channel hole 12A.Due to the cell channel hole 15 and the pipe channel hole 12A, the twostrings have a U-shaped string structure. A charge storage or chargetrapping layer 16, a cell channel 17, and a second insulation layer 18are buried in the cell channel hole 15. The charge storage or chargetrapping layer 16 includes a blocking layer, a charge trap layer, and atunnel insulation layer which are sequentially stacked. The cell channel17 has a pair of columnar structures. The pipe channel 17A couples thebottoms of a pair of cell channels 17. The control gate electrodes 14 ofthe first string MS1 and the control gate electrodes 14 of the secondstring MS2 are separated from each other by a slit 19.

In the conventional nonvolatile memory device of FIG. 1, the number oflayers of the cell stack must increase in order to increase cellintensity. However, as the number of layers of the cell stack increases,it becomes more difficult to apply a contact etching process and a slitetching process for forming the slit 19. In particular, in the case ofthe slit etching process, the damage 20 of the pipe gate 12 shouldideally be prevented.

However, as the number of layers of the cell stack increases, it islikely that the pipe gate 12 is damaged as indicated by referencenumeral 20.

In order to address this concern, a passivation layer may be formed onthe pipe gate 12 upon the etching of the cell stack. In this case,however, the gap between the lowermost control gate electrode 14 and thepipe gate 12 increases, thereby lowering the current supplied when acell is in an “on” state.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to anonvolatile memory device, which is capable of preventing a lower pipegate from being damaged during a slit etching process for separatingcontrol gate electrodes from each other, and preventing a currentsupplied when a cell is in an “on” state from being lowered, and amethod for fabricating the same.

In accordance with an exemplary embodiment of the present invention, anonvolatile memory device includes a pipe insulation layer having a pipechannel hole, a pipe gate disposed over the pipe insulation layer, apair of cell strings each having a columnar cell channel, and a pipechannel coupling the columnar cell channels and surrounding innersidewalls and a bottom of the pipe channel hole.

In accordance with another exemplary embodiment of the presentinvention, a nonvolatile memory device includes a first pipe gate havinga pipe channel hole, a second pipe gate disposed over the first pipegate, a pair of cell strings each having a columnar cell channel, and apipe channel coupling the columnar cell channels and surrounding innersidewalls and a bottom of the pipe channel hole.

In accordance with yet another exemplary embodiment of the presentinvention, a method for fabricating a nonvolatile memory device includesforming a pipe insulation layer in which a sacrificial layer is buried,forming a pipe gate over the pipe insulation layer, forming a cell stackhaving a pair of cell channel holes, removing the sacrificial layer toform a pipe channel hole, forming a pair of columnar cell channels and apipe channel by partially filling the cell channel holes and the pipechannel hole, and forming a slit which separates the cell stack intocell strings.

In accordance with still another exemplary embodiment of the presentinvention, a method for fabricating a nonvolatile memory device includesforming a first pipe gate in which a sacrificial layer is buried;forming a second pipe gate and a cell stack having a pair of cellchannel holes, removing the sacrificial layer to form a pipe channelhole, forming a pair of columnar cell channels and a pipe channel bypartially filling the cell channel holes and the pipe channel hole, andforming a slit which separates the cell stack into cell strings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional nonvolatile memorydevice.

FIG. 2A is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a first exemplaryembodiment of the present invention.

FIG. 2B is an equivalent circuit diagram of the nonvolatile memorydevice in accordance with the first exemplary embodiment of the presentinvention.

FIG. 2C is a plan view of the nonvolatile memory device in accordancewith the first exemplary embodiment of the present invention.

FIGS. 3A to 3J are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the firstexemplary embodiment of the present invention.

FIG. 3K is a diagram of the nonvolatile memory device in accordance withthe first exemplary embodiment of the present invention illustratingpossible connections.

FIG. 4 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a second exemplaryembodiment of the present invention.

FIGS. 5A to 5H are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the secondexemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a third exemplaryembodiment of the present invention.

FIGS. 7A to 7K are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the thirdexemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a fourth exemplaryembodiment of the present invention.

FIGS. 9A to 9F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the fourthexemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a fifth exemplaryembodiment of the present invention.

FIGS. 11A to 11I are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with a fifthexemplary embodiment of the present invention.

FIG. 11J illustrates a modification of the fifth exemplary embodiment.

FIG. 12 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a sixth exemplaryembodiment of the present invention.

FIGS. 13A to 13F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the sixthexemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a seventh exemplaryembodiment of the present invention.

FIGS. 15A to 15F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with a seventhexemplary embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate, but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

In the exemplary embodiments, a memory cell may have a three-dimensionalstructure, such as a silicon-oxide-nitride-oxide-silicon (SONOS)structure or metal-oxide-nitride-oxide-silicon (MONOS) structure.

FIG. 2A is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a first exemplaryembodiment of the present invention. FIG. 2B is an equivalent circuitdiagram of the nonvolatile memory device in accordance with the firstexemplary embodiment of the present invention. FIG. 2C is a plan view ofthe nonvolatile memory device in accordance with the first exemplaryembodiment of the present invention. FIG. 2A is a cross-sectional viewtaken along line A-A′ of FIG. 2C.

Referring to FIGS. 2A to 2C, the nonvolatile memory device includes apair of cell channels 32A protruding from a substrate 21, a first pipechannel 32B coupling the bottoms of the pair of the cell channels 32A,second pipe channels 32C coupling the first pipe channel 32B and thecell channels 32A, a first pipe gate 23A in which the first pipe channel32B is buried, a second pipe gate 26B surrounding the second pipechannels 32C, and second insulation patterns 27B and control gateelectrodes 28B surrounding the cell channels 32A. The control gateelectrodes 28B between the cell channels 32A are separated from oneanother by a slit 34.

Specifically, a first insulation layer 22 is formed between thesubstrate 21 and the first pipe gate 23A. The first insulation layer 22may include an oxide layer, such as a silicon oxide layer. The substrate21 may include a silicon substrate. The first pipe gate 23A may includea silicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 32A, the first pipe channel 32B, and the second pipechannels 32C are formed of the same material. For example, the cellchannels 32A, the first pipe channel 32B, and the second pipe channels32C may include a polysilicon layer, specifically, an undopedpolysilicon layer. The cell channels 32A, the first pipe channel 32B,and the second pipe channels 32C collectively form a U-shaped structure.

The cell channels 32A and the second pipe channels 32C fill cell channelholes 29, and the first pipe channel 32B fills a pipe channel hole 24.The cell channel holes 29 pass through a cell stack 102 in which thecontrol gate electrodes 28B and second insulation patterns 27B arealternately stacked. The pipe channel hole 24 is formed by etching thefirst pipe gate 23A. A third insulation pattern 33A and a charge storageor charge trapping layer 31A are further formed in the cell channelholes 29 and the pipe channel hole 24. The charge storage or chargetrapping layer 31A is formed between the cell channel 32A and thecontrol gate electrode 28B, and the third insulation pattern 33A fillsthe cell channel holes 29 inside of the cell channels 32A. The chargestorage or charge trapping layer 31A includes a blocking layer, a chargetrap layer, and a tunnel insulation layer. The third insulation pattern33A includes an oxide layer, such as a silicon oxide layer. A silicide35 is formed on a sidewall of the control gate electrode 28B.

The second pipe gate 26B is formed under the lowermost control gateelectrode 28B, and a passivation pattern 25C is disposed between thesecond pipe gate 26B and the first pipe gate 23A. The passivationpattern 25C includes a nitride layer such as a silicon nitride layer.The passivation pattern 25C prevents the first pipe channel 32B and thefirst pipe gate 23A from being damaged during the formation of the slit34.

Two memory strings MS1 and MS2 are formed by the slit 34. A first pipechannel transistor PCTr1 is formed by the first pipe gate 23A and thefirst pipe channel 32B, and two second pipe channel transistors PCTr2are formed by the second pipe gate 26B and the second pipe channels 32C.The two memory strings MS1 and MS2 are coupled to the first and secondpipe channel transistors PCTr1 and PCTr2. The first pipe channeltransistor PCTr1 and the second pipe channel transistors PCTr2 arecoupled in series. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the first and second pipe channel transistorsPCTr1 and PCTr2 to thereby constitute a single memory cell string. Forexample, where three memory cells are formed in each memory string, thesingle memory cell string includes six memory cells.

Referring to FIG. 2B, the nonvolatile memory device in accordance withthe first exemplary embodiment of the present invention includes twomemory strings MS1 and MS2, two second pipe channel transistors PCTr2,and one first pipe channel transistor PCTr1. In addition, thenonvolatile memory device includes a source select transistor SSTr and adrain select transistor SDTr. The drain select transistor SDTr iscoupled to a bit line BL, and the source select transistor SSTr iscoupled to a source line SL. Further, although FIG. 2B shows the sourceselect transistor SSTr coupled to the second memory string MS2 and thedrain select transistor SDTr coupled to the first memory string MS1, thenonvolatile memory device may be constructed vice versa. That is, thesource select transistor SSTr may be coupled to the first memory stringMS1 and the drain select transistor SDTr may be coupled to the secondmemory string MS2. The source select transistor SSTr, the drain selecttransistor SDTr, the bit line BL, and the source line SL are notillustrated in FIG. 2A. Gates of the first pipe channel transistor PCTr1and the second pipe channel transistor PCTr2 are commonly coupled, and asignal PC1 is commonly inputted therethrough. Reference symbol “SGD”represents a signal which is applied to the gate of the drain selecttransistor SDTr, and reference symbol “SGS” represents a signal which isapplied to the gate of the source select transistor SSTr.

The first memory string MS1 includes three memory cells MC1, MC2 and MC3coupled to word lines WL1 to WL3, and the second memory string MS2includes three memory cells MC4, MC5 and MC6 coupled to word lines WL4to WL6.

FIGS. 3A to 3J are cross-sectional views illustrating a method forfabricating a three-dimensional nonvolatile memory device in accordancewith the first exemplary embodiment of the present invention. FIGS. 3Ato 3J are cross-sectional views taken along line A-A′ of FIG. 2C.

Referring to FIG. 3A, a first conductive layer 23 is formed on asubstrate 21. The substrate 21 may include a silicon substrate. A firstinsulation layer 22 is formed between the substrate 21 and the firstconductive layer 23. The first insulation layer 22 may include an oxidelayer. The first conductive layer 23 may include a silicon layer, inparticular, an N⁺ polysilicon layer. The first conductive layer 23 isused as a first pipe gate.

Referring to FIG. 3B, the first conductive layer 23 is etched to form apipe channel hole 24. As a result of the etch, a first pipe gate 23A isformed. In order to form the pipe channel hole 24, the first conductivelayer 23 may be etched using an anisotropic etching process or anisotropic etching process. In this embodiment, the pipe channel hole 24is formed using an isotropic etching process.

Referring to FIG. 3C, a sacrificial layer 24A is formed to gap-fill thepipe channel hole 24. The sacrificial layer 24A includes an insulationlayer, such as, for example, an oxide layer. After forming thesacrificial layer 24A over a resulting structure until it gap-fills thepipe channel hole 24, a planarization process, such as a chemicalmechanical polishing (CMP) process, may be performed. The CMP process isstopped at the first pipe gate 23A.

A passivation layer 25 is formed over a resulting structure, includingthe sacrificial layer 24A and the first pipe gate 23A. The passivationlayer 25 is used as an etch stop layer during a subsequent slit etchingprocess. The passivation layer 25 may include a nitride layer.

A second conductive layer 26 is formed on the passivation layer 25. Thesecond conductive layer 26 may include a silicon layer, in particular,an N⁺ polysilicon layer. The second conductive layer 26 is used as asecond pipe gate.

Referring to FIG. 3D, a cell stack 100, in which second insulationlayers 27 and third conductive layers 28 are alternately stacked, isformed on the second conductive layer 26. The second insulation layers27 separate control gate electrodes of a plurality of memory cellsstacked over the substrate 21. The second insulation layers 27 mayinclude an oxide layer. The uppermost layer of the cell stack 100 is thesecond insulation layer 27. Also, the third conductive layers 28 areused as the control gate electrodes of the memory cells, and therefore,may include a polysilicon layer doped with a P-type impurity or N-typeimpurity. In this exemplary embodiment, the third conductive layers 28include a polysilicon layer doped with a P-type impurity, that is, a P⁺polysilicon layer. The second insulation layers 27 and the thirdconductive layers 28 are repetitively formed according to the number ofthe memory cells desired to be stacked. Although any number of memorycells may be stacked, for convenience of explanation, with regards tothe first exemplary embodiment of the present invention, the memorystrings each include three stacked memory cells, and therefore, thememory cell string includes six memory cells. Furthermore, a thirdconductive layer for a select transistor may be further stacked althoughits illustration is omitted.

Referring to FIG. 3E, the cell stack 100 is etched to form two cellchannel holes 29 exposing two separate portions of the surface of thesacrificial layer 24A. The cell channel holes 29 are formed to passthrough the cell stack 100, the second conductive layer 26, and thepassivation layer 25. As a result of forming the cell channel holes 29,a cell stack 101 having a structure in which second insulation patterns27A and third conductive patterns 28A are alternately stacked, apassivation pattern 25A, and a second conductive pattern 26A are formed.The cell channel holes 29 pass through the second insulation patterns27A, the third conductive patterns 28A, the second conductive pattern26A, and the passivation pattern 25A. Before forming the cell channelholes 29, the ends of the third conductive patterns 28A may be etchedusing, for example, a slimming etching process, to form a stepped shapestructure (not illustrated). The stepped portions may become a contactregion between a word line and a control gate electrode.

Referring to FIG. 3F, spacers 30 are formed on both sidewalls of thecell channel holes 29. The spacers 30 are formed by depositing a nitridelayer and performing an etch-back process on the deposited nitridelayer. The spacers 30 expose the surface of the sacrificial layer 24A,and protect both sidewalls of the cell channel holes 29.

Next, the sacrificial layer 24A is removed. Accordingly, the pipechannel hole 24 is again opened. The spacers 30 protect the thirdconductive patterns 28A, the second insulation patterns 27A, the secondconductive pattern 26A, and the passivation pattern 25A, while thesacrificial layer 24A is removed.

More specifically, the sacrificial layer 24A is removed such that thepipe channel hole 24 forms an opening between the adjacent cell channelholes 29. Thus, the cell channel holes 29 and the pipe channel hole 24collectively form a U-shaped opening.

Referring to FIG. 3G, the spacers 30 are removed. When removing thespacers 30, the passivation pattern 25A using the nitride layer may alsobe partially removed. The remaining passivation pattern is indicated byreference numeral “25B”. The spacers 30 may be removed by a wet process,in particular, a wet strip process. Accordingly, only the spacers 30formed of nitride may be selectively removed without causing damage tothe third conductive patterns 28A and the second insulation patterns27A.

Referring to FIG. 3H, after removing the spacers 30, a charge storage orcharge trapping layer 31 is formed on the resulting structure, includingthe pipe channel hole 24. Preferably, the charge storage or chargetrapping layer 31 is formed to conform to cover all surfaces exposed bythe cell channel holes 29 and pipe channel hole 24. The charge storageor charge trapping layer 31 may include a blocking layer, a charge traplayer, and a tunnel insulation layer. That is, the charge storage orcharge trapping layer 31 may be formed by sequentially stacking theblocking layer, the charge trap layer, and the tunnel insulation layer.The blocking layer prevents charges from passing through the charge traplayer and moving toward the gate electrode. The blocking layer mayinclude an oxide layer formed by a thermal oxidation process or adeposition process. The tunnel insulation layer may include an oxidelayer, such as a silicon oxide layer. The charge trap layer is used asan actual data storage and includes a charge trap layer which trapscharges in a deep level trap site. The charge trap layer may include anitride layer. Therefore, the charge storage or charge trapping layer 31may have an oxide-nitride-oxide (ONO) structure.

A fourth conductive layer 32 is formed on the charge storage or chargetrapping layer 31. Preferably, the fourth conductive layer 32 is formedto conform to cover all surfaces exposed by the cell channel holes 29and pipe channel hole 24. The fourth conductive layer 32 may include asilicon layer. In particular, the fourth conductive layer 32 includes apolysilicon layer, specifically, an undoped polysilicon layer. Thefourth conductive layer 32 is used as a cell channel of the memory cell.

A third insulation layer 33 is formed on the fourth conductive layer 32.The third insulation layer 33 may include an oxide layer. The thirdinsulation layer 33 is formed to gap-fill the cell channel holes 29.However, when forming the third insulation layer 33, the bottom of thecell channel hole 29 is sealed, before the pipe channel hole 24 iscompletely filled. Accordingly, a hollow region is formed inside thepipe channel hole 24.

Referring to FIG. 3I, a planarization process is performed to expose theuppermost second insulation pattern 27A of the cell stack 101. Theplanarization process may include a CMP process. Specifically, the thirdinsulation layer 33, the fourth conductive layer 32, and the chargestorage or charge trapping layer 31 are planarized.

Due to such a planarization process, the fourth conductive layer 32becomes the columnar cell channels 32A, which are formed within the cellchannel holes 29, the charge storage or charge trapping layer 31 becomesthe planarized charge storage or charge trapping layer 31A, and thethird insulation layer 33 becomes the third insulation pattern 33A.Also, a first pipe channel 32B is formed within the pipe channel hole24. A second pipe channel 32C is formed to couple the cell channel 32Aand the first pipe channel 32B. Further, the first and second pipechannels 32B and 32C couple the cell channels 32A of adjacent memorystrings MS1 and MS2.

Accordingly, the cell channel 32A, the first pipe channel 32B, and thesecond pipe channel 32C collectively form a U-shaped structure. Also,even after the planarization process, the third insulation pattern 33Aremains to form a hollow region 33B inside of the pipe channel hole 24.

A slit etching process is performed in order to separate the controlgate electrodes 28B between the adjacent memory strings MS1 and MS2. Asa result, a slit 34 is formed. In order to form the slit 34, the secondinsulation patterns 27A, the third conductive patterns 28A, and thesecond conductive pattern 26A are sequentially etched, and the etchingis stopped at the passivation pattern 25B. A portion of the passivationpattern 25B may be removed, leaving the remaining passivation pattern25C. However, since the passivation pattern 25B sufficiently serves asthe etch stop layer, the slit 34 does not pass through the underlyingpipe channel 32B.

As such, when the slit 34 is formed, the cell stack is separated asindicated by reference numeral “102”. The separated cell stack 102becomes two memory strings MS1 and MS2 in which the second insulationpatterns 27B and the control gate electrodes 28B are alternatelystacked. The memory strings MS1 and MS2 include the charge storage orcharge trapping layers 31A and the cell channels 32A buried in the cellchannel holes 29.

A second pipe gate 26B is formed between the memory strings MS1 and MS2and the first pipe gate 23A, and the passivation pattern 25C remainsbetween the second pipe gate 26B and the first pipe gate 23 k Theadjacent cell channels 32A are coupled together through the first andsecond pipe channels 32B and 32C. The first pipe channel 32B is buriedwithin the pipe channel hole 24, and the second pipe channel 32C isburied in the cell channel holes 29 under the memory strings MS1 andMS2. The regions between the first pipe channel 32B and the regionsbetween the second pipe channel 32C may be empty. That is, the thirdinsulation pattern 33A may not be between the first pipe channel 32B andthe second pipe channel 32C. The second pipe gate 26B and the secondpipe channel 32C form a second pipe channel transistor PCTr2, and thefirst pipe gate 23A and the first pipe channel 32B form a first pipechannel transistor PCTr1.

Due to the passivation pattern 25C, the first pipe channel 32B and thefirst pipe gate 23A are not damaged during the slit etching process.

Referring to FIG. 3J, a silicide 35 is formed on a sidewall of thecontrol gate electrodes 28B exposed by the slit 34.

In accordance with the first exemplary embodiment described above, theetching is stopped by at least the passivation pattern 25C during theslit etching process for forming the slit 34. Accordingly, the damage ofthe first pipe channel 32B and the first pipe gate 23A is prevented,thereby improving an etching margin. In the first exemplary embodiment,although the etching is stopped in the passivation pattern 25C duringthe slit etching process, the etching may also be stopped in any one ofthe passivation pattern 25C, the second pipe gate 26B, and the lowermostthird insulation pattern 27B.

In the first exemplary embodiment, as the passivation pattern 25C isinserted, the channel length between the lowermost memory cell and thefirst pipe channel transistor PCTr1 may increase. However, the increasein the channel distance is prevented by forming the second pipe gate 26Band the second pipe channel 32C under the memory string. Thus, the cellon current is not lowered. Herein, the “cell on current” refers to thecurrent flowing through a single memory cell string, including twomemory strings, when a selected memory cell of the memory cell string isin the “on” state.

FIG. 3K is a diagram of the nonvolatile memory device in accordance withthe first exemplary embodiment of the present invention illustratingpossible connections. FIG. 3K is a cross-sectional view taken along lineB-B′ of FIG. 2C.

Referring to FIG. 3K, the ends of the control gate electrodes 28B areformed in a stepped shape. Word lines 38 for applying word line signalsare coupled to respective control gate electrodes 28B. The first pipegate 23A and the second pipe gate 26B are commonly coupled by a singlemetal interconnection 39. More specifically, the word lines 38 and themetal interconnection 39 are coupled to corresponding plugs 37 passingthrough an interlayer dielectric layer 36.

The semiconductor memory device in accordance with the first exemplaryembodiment of the present invention includes the first pipe gate 23A andthe second pipe gate 26B. The etching is stopped by at least thepassivation pattern 25C during the etching of the slit 34. Furthermore,the increase in the channel distance is compensated for by furtherforming the second pipe gate 26B under the memory strings.

FIG. 4 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a second exemplaryembodiment of the present invention.

Referring to FIG. 4, the nonvolatile memory device includes a pair ofcell channels 51A protruding from a substrate 41, a first pipe channel51B coupling the bottoms of the pair of the cell channels 51A, secondpipe channels 51C coupling the first pipe channel 51B and the cellchannels 51A, a first pipe gate 43A in which the first pipe channel 51Bis buried, a second pipe gate 46B surrounding the second pipe channels51C, and control gate electrodes 48B surrounding the cell channels 51A.The control gate electrodes 48B between the cell channels 51A areseparated from one another by a slit 53.

Specifically, a first insulation layer 42 is formed between thesubstrate 41 and the first pipe gate 43A. The first insulation layer 42may include an oxide layer, such as a silicon oxide layer. The substrate41 may include a silicon substrate. The first pipe gate 43A may includea silicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 51A, the first pipe channel 51B, and the second pipechannels 51C are formed of the same material. For example, the cellchannels 51A, the first pipe channel 51B, and the second pipe channels51C may include a polysilicon layer, specifically, an undopedpolysilicon layer. The cell channels 51A, the first pipe channel 51B,and the second pipe channels 51C collectively form a U-shaped structure.

The cell channels 51A and the second pipe channels 51C fill cell channelholes 49, and the first pipe channel 51B fills a pipe channel hole 44.The cell channel holes 49 pass through a cell stack 202 in which thecontrol gate electrodes 48B and third insulation patterns 47B arealternately stacked. The pipe channel hole 44 is formed by etching thefirst pipe gate 43A. A fourth insulation pattern 52A and a chargestorage or charge trapping layer 50A are further formed in the cellchannel holes 49 and the pipe channel hole 44. The charge storage orcharge trapping layer 50A is formed between the cell channel 51A and thecontrol gate electrode 48B, and the fourth insulation pattern 52A fillsthe cell channel holes 49 inside of the cell channels 51A. The chargestorage or charge trapping layer 50A includes a blocking layer, a chargetrap layer, and a tunnel insulation layer. The fourth insulation pattern52A includes an oxide layer, such as a silicon oxide layer.

The second pipe gate 46B is formed under the lowermost control gateelectrode 48B, and a second insulation pattern 45A is disposed betweenthe second pipe gate 46B and the first pipe gate 43A. The secondinsulation pattern 45A may include an oxide layer, such as a siliconoxide layer. The second insulation pattern 45A prevents the first pipechannel 51B and the first pipe gate 43A from being damaged during theformation of the slit 53.

Two memory strings MS1 and MS2 are formed by the slit 53. A first pipechannel transistor PCTr1 is formed by the first pipe gate 43A and thefirst pipe channel 51B, and two second pipe channel transistors PCTr2are formed by the second pipe gate 46B and the second pipe channels 51C.The two memory strings MS1 and MS2 are coupled to the first and secondpipe channel transistors PCTr1 and PCTr2. The first pipe channeltransistor PCTr1 and the second pipe channel transistors PCTr2 arecoupled in series. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the first and second pipe channel transistorsPCTr1 and PCTr2 to thereby constitute a single memory cell string. Forexample, where three memory cells are formed in each memory string, thesingle memory cell string includes six memory cells.

FIGS. 5A to 5H are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the secondexemplary embodiment of the present invention. FIGS. 5A to 5H arecross-sectional views taken along the same direction as that of the lineA-A′ of FIG. 2C.

Referring to FIG. 5A, a first conductive layer 43 is formed on asubstrate 41. The substrate 41 may include a silicon substrate. A firstinsulation layer 42 is formed between the substrate 41 and the firstconductive layer 43. The first insulation layer 42 may include an oxidelayer, such as a silicon oxide layer. The first conductive layer 43 mayinclude a silicon layer, in particular, an N⁺ polysilicon layer. Thefirst conductive layer 43 is used as a first pipe gate.

Referring to FIG. 5B, the first conductive layer 43 is etched to form apipe channel hole 44. As a result of the etch, a first pipe gate 43A isformed. In order to form the pipe channel hole 44, the first conductivelayer 43 may be etched using an anisotropic etching process or anisotropic etching process. In this embodiment, the pipe channel hole 44is formed using an isotropic etching process.

Referring to FIG. 5C, a sacrificial layer 44A is formed to gap-fill thepipe channel hole 44. The sacrificial layer 44A includes an insulationlayer, such as, for example, a silicon nitride layer. After forming thesacrificial layer 44A over a resulting structure until it gap-fills thepipe channel hole 44, a planarization process, such as a chemicalmechanical polishing (CMP) process, may be performed.

A second insulation layer 45 is formed over a resulting structure,including the sacrificial layer 44A and the first pipe gate 43A. Thesecond insulation layer 45 serves as an insulation layer between thefirst pipe gate 43A and a subsequently formed second pipe gate. Also,the second insulation layer 45 is used as a passivation layer during asubsequent slit etching process. The second insulation layer 45 mayinclude an oxide layer, such as a silicon oxide layer. The secondinsulation layer 45 is formed to a minimal thickness in order tofunction as insulation between the first pipe gate 43A and the secondpipe gate.

A second conductive layer 46 is formed on the second insulation layer45. The second conductive layer 46 may include a silicon layer, inparticular, an N⁺ polysilicon layer. The second conductive layer 46 isused as a second pipe gate.

Referring to FIG. 5D, a cell stack 200, in which third insulation layers47 and third conductive layers 48 are alternately stacked, is formed onthe second conductive layer 46. The third insulation layers 47 separatecontrol gate electrodes of a plurality of memory cells stacked over thesubstrate 41. The third insulation layers 47 may include an oxide layer.The uppermost layer of the cell stack 200 is the third insulation layer47. Also, the third conductive layers 48 are used as the control gateelectrodes of the memory cells, and therefore, may include a polysiliconlayer doped with a P-type impurity or N-type impurity. In this exemplaryembodiment, the third conductive layers 48 include a polysilicon layerdoped with a P-type impurity, that is, a P⁺ polysilicon layer. The thirdinsulation layers 47 and the third conductive layers 48 are repetitivelyformed according to the number of the memory cells desired to bestacked. Although any number of memory cells may be stacked, forconvenience of explanation, with regards to the second exemplaryembodiment of the present invention, the memory strings each includethree stacked memory cells, and therefore, the memory cell stringincludes six memory cells.

Referring to FIG. 5E, the cell stack 200 is etched to form two cellchannel holes 49 exposing two separate portions of the surface of thesacrificial layer 44A. The cell channel holes 49 are formed to passthrough the cell stack 200, the second conductive layer 46, and thesecond insulation layer 45. As a result of forming the cell channelholes 49, a cell stack 201 having a structure in which third insulationpatterns 47A and third conductive patterns 48A are alternately stacked,a second insulation pattern 45A, and a second conductive pattern 46A areformed.

The cell channel holes 49 pass through the third insulation patterns47A, the third conductive patterns 48A, the second conductive pattern46A, and the second insulation pattern 45A. Before forming the cellchannel holes 49, the ends of the third conductive patterns 48A may beetched using, for example, a slimming etching process, to form a steppedshape structure (not illustrated). Meanwhile, a lower end of the cellchannel holes 49 may extend up to the sacrificial pattern 44A. However,since a sacrificial pattern 44A serves as a passivation layer, the cellchannel holed 49 do not pass through the first pipe gate 43A, but ratherstop in the sacrificial pattern 44A.

Referring to FIG. 5F, the sacrificial layer 44A is removed. Accordingly,the pipe channel hole 44 is again opened.

The sacrificial layer 44A may be removed by a wet process, inparticular, a wet strip process. Accordingly, only the sacrificial layer44A formed of nitride may be selectively removed without causing damageto the third conductive patterns 48A, the third insulation pattern 47A,the second conductive pattern 46A, and the second insulation pattern45A.

Referring to FIG. 5G, after removing the sacrificial layer 44A, a chargestorage or charge trapping layer 50 is formed on the resultingstructure, including the pipe channel hole 44. Preferably, the chargestorage or charge trapping layer is formed to cover all surfaces exposedby the cell channel holes 49 and the pipe channel hole 44. The chargestorage or charge trapping layer 50 may include a blocking layer, acharge trap layer, and a tunnel insulation layer. That is, the chargestorage or charge trapping layer 50 may be formed by sequentiallystacking the blocking layer, the charge trap layer, and the tunnelinsulation layer. The blocking layer prevents charges from passingthrough the charge trap layer and moving toward the gate electrode. Theblocking layer may include an oxide layer formed by a thermal oxidationprocess or a deposition process. The tunnel insulation layer may includean oxide layer, such as a silicon oxide layer. The charge trap layer isused as an actual data storage and includes a charge trap layer whichtraps charges in a deep level trap site. The charge trap layer mayinclude a nitride layer.

A fourth conductive layer 51 is formed on the charge storage or chargetrapping layer 50. Preferably, the fourth conductive layer 51 is formedto conform to cover all surfaces exposed by the cell channel holes 49and pipe channel hole 44. The fourth conductive layer 51 may include asilicon layer. In particular, the fourth conductive layer 51 includes apolysilicon layer, specifically, an undoped polysilicon layer. Thefourth conductive layer 51 is used as a cell channel of the memory cell.

A fourth insulation layer 52 is formed on the fourth conductive layer51. The fourth insulation layer 52 includes an oxide layer. The fourthinsulation layer 52 is formed to gap-fill the cell channel holes 49.

Referring to FIG. 5H, a planarization process is performed to expose theuppermost third insulation pattern 47A of the cell stack 201. Theplanarization process may include a CMP process. Specifically, thefourth insulation layer 52, the fourth conductive layer 51, and thecharge storage or charge trapping layer 50 are planarized.

Due to such a planarization process, the fourth conductive layer 51becomes the columnar cell channels 51A, which are formed within the cellchannel holes 49, the charge storage or charge trapping layer 50 becomesthe planarized charge storage or charge trapping layer 50A, and thefourth insulation layer 52 becomes the fourth insulation pattern 52A.Also, a first pipe channel 51B is formed within the pipe channel hole44. Two second pipe channels 51C are formed to couple the cell channel51A and the first pipe channel 51B. Further, the first and second pipechannels 51B and 51C couple the cell channels 51A of adjacent memorystrings MS1 and MS2. Accordingly, the cell channels 51A, the first pipechannel 51B, and the second pipe channels 51C collectively form aU-shaped structure. Also, even after the planarization process, thefourth insulation pattern 52A remains to form a hollow region inside ofthe pipe channel hole 44.

A slit etching process is performed in order to separate the controlgate electrodes 48B between the adjacent memory strings MS1 and MS2. Asa result, a slit 53 is formed. Due to the slit 53, the cell stack isseparated as indicated by reference numeral “202”. In order to form theslit 53, the third insulation patterns 47A, the third conductivepatterns 48A, and the second conductive pattern 46A are sequentiallyetched, and the etching is stopped at the second conductive pattern 46A.A portion of the second conductive pattern 46A may be removed, leavingthe remaining second conductive patter 46B. However, the slit 53 doesnot pass through the underlying first pipe channel 51B.

As such, when the slit 53 is formed, two memory strings MS1 and MS2 inwhich the third insulation patterns 47B and the control gate electrodes48B are alternately stacked are formed. The memory strings MS1 and MS2include the charge storage or charge trapping layers 50A and the cellchannels 51A buried in the cell channel holes 49.

A second pipe gate 46B is formed between the memory strings MS1 and MS2and the first pipe gate 43A, and the second insulation pattern 45Aremains between the second pipe gate 46B and the first pipe gate 43A.The adjacent cell channels 51A are coupled together through the firstand second pipe channels 51B and 51C. The first pipe channel 51B isburied within the pipe channel hole 44, and the second pipe channel 52Cis buried in the cell channel holes 49 under the memory strings MS1 andMS2. The second pipe gate 46B and the second pipe channels 51C form twosecond pipe channel transistor PCTr2, and the first pipe gate 43A andthe first pipe channel 51B form a first pipe channel transistor PCTr1.

Due to at least the second pipe gate 46B, the first pipe channel 51B andthe first pipe gate 43A are not damaged during the slit etching process.In other words, the etching may be stopped at any one of the second pipegate 46B, the second insulation pattern 45A, and the lowermost thirdinsulation pattern 47B during the slit etching process. Therefore, thefirst pipe channel 51B and the first pipe gate 43A are not damaged. Thesecond insulation pattern 45A serves as the passivation layer just likethe passivation pattern of the first exemplary embodiment which isformed of nitride.

A silicide (not shown) is formed on a sidewall of the control gateelectrodes 48B exposed by the slit 53.

The semiconductor memory device in accordance with the second exemplaryembodiment of the present invention includes the first pipe gate 43A andthe second pipe gate 46B.

In the second exemplary embodiment, the etching is stopped by at leastthe second pipe gate 46B during the slit etching process for forming theslit 53. Accordingly, the damage of the first pipe channel 51B and thefirst pipe gate 43A is prevented, thereby improving an etching margin.

In the second exemplary embodiment, as the second insulation pattern 45Ais inserted under the second pipe gate 46B, the channel length betweenthe lowermost memory cell and the first pipe channel transistor PCTr1may increase. However, the increase in the channel distance is preventedby forming the second insulation pattern 45A thinly and forming thesecond pipe gate 46B and the second pipe channel 51C under the memorystring. Thus, the cell on current is not lowered.

FIG. 6 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a third exemplaryembodiment of the present invention.

Referring to FIG. 6, the nonvolatile memory device includes a pair ofcell channels 71A protruding from a substrate 61, a first pipe channel71B coupling the bottoms of the pair of the cell channels 71A, a firstpipe gate 63A in which the first pipe channel 71B is buried, a secondpipe gate 75B surrounding the bottoms of the cell channels 71A, andcontrol gate electrodes 75A surrounding the cell channels 71A. Thecontrol gate electrodes 75A between the cell channels 71A are separatedfrom one another by a slit 72. The bottoms of the cell channels 71Asurrounded by the second pipe gate 75B become a second pipe channel 71C.

Specifically, a first insulation layer 62 is formed between thesubstrate 61 and the first pipe gate 63A. The first insulation layer 62may include an oxide layer, such as a silicon oxide layer. The substrate61 may include a silicon substrate. The first pipe gate 63A may includea silicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 71A, the first pipe channel 71B, and the second pipechannels 71C are formed of the same material. For example, the cellchannels 71A, the first pipe channel 71B, and the second pipe channels71C may include a polysilicon layer, specifically, an undopedpolysilicon layer. The cell channels 71A, the first pipe channel 71B,and the second pipe channels 71C collectively form a U-shaped structure.

The cell channels 71A have a columnar structure, the first pipe channel71B fills the pipe channel hole 65 within the first pipe gate 63A. Thecell channels 71A are surrounded by the control gate electrodes 75A andthe second insulation patterns 69B, which are alternately stacked. Thefirst pipe gate 63A has a pipe channel hole 65, and a pipe tunnelinsulation layer 66 is formed on the surface of the pipe channel hole65. The control gate electrodes 75A fill undercuts 73 formed between thesecond insulation patterns 69B. A charge storage or charge trappinglayer 74A is formed between the control gate electrodes 75A and the cellchannels 71A. The charge storage or charge trapping layer 74A includes ablocking layer, a charge trap layer, and a tunnel insulation layer. Thelowermost control gate electrode becomes a second pipe gate 75B.

Two memory strings MS1 and MS2 are formed by the slit 72. A first pipechannel transistor PCTr1 is formed by the first pipe gate 63A and thefirst pipe channel 71B, and two second pipe channel transistors PCTr2are formed by the second pipe gate 75B and the second pipe channels 71C.The two memory strings MS1 and MS2 are coupled to the first and secondpipe channel transistors PCTr1 and PCTr2. The first pipe channeltransistor PCTr1 and the second pipe channel transistors PCTr2 arecoupled in series. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the first and second pipe channel transistorsPCTr1 and PCTr2 to thereby constitute a single memory cell string. Forexample, where three memory cells are formed in each memory string, thesingle memory cell string includes six memory cells.

FIGS. 7A to 7K are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the thirdexemplary embodiment of the present invention. FIGS. 7A to 7K arecross-sectional views taken along the same direction as that of the lineA-A′ of FIG. 2C.

Referring to FIG. 7A, a first conductive layer 63 is formed on asubstrate 61. The substrate 61 may include a silicon substrate. A firstinsulation layer 62 is formed between the substrate 61 and the firstconductive layer 61. The first insulation layer 62 may include a nitridelayer, such as a silicon oxide layer. The first conductive layer 63 mayinclude a silicon layer, in particular, an N⁺ polysilicon layer. Thefirst conductive layer 63 is used as a first pipe gate.

Referring to FIG. 7B, a polishing stop layer is formed on the firstconductive layer 63. Then, the polishing stop layer and the firstconductive layer 63 are etched to form a pipe channel hole 65. As aresult, a first pipe gate 63A and a polishing stop pattern 64 areformed. In order to form the pipe channel hole 65, the first conductivelayer 63 and polishing stop layer may be etched using an anisotropicetching process or an isotropic etching process. In this embodiment, thepipe channel hole 65 is formed using an isotropic etching process. Thepolishing stop pattern 64 may include an oxide layer, such as a siliconoxide layer.

Referring to FIG. 7C, a pipe gate tunnel insulation layer 66 is formedon a resulting structure including the pipe channel hole 65. The pipegate tunnel insulation layer 66 may include an oxide layer, such as asilicon oxide layer.

A first sacrificial layer 67 gap-filling the pipe channel hole 65 isformed on the pipe gate tunnel insulation layer 66. The firstsacrificial layer 67 includes amorphous silicon or a silicon germaniumcompound. After forming the first sacrificial layer 67 over a resultingstructure until it gap-fills the pipe channel hole 65, a planarizationprocess, such as a chemical mechanical polishing (CMP) process, may beperformed. In the planarization process, the planarizing is stopped atthe pipe gate tunnel insulation layer 66. Performing the planarizationprocess until the pipe gate tunnel insulation layer 66 is reachedresults in the formation of the first sacrificial pattern 67A.

Referring to FIG. 7D, an insulation layer stack 300, in which secondsacrificial layers 68 and second insulation layers 69 are alternatelystacked, is formed on a resulting structure including the firstsacrificial pattern 67A. The second sacrificial layers 68 include anitride layer, such as a silicon nitride layer. The uppermost layer ofthe insulation layer stack 300 is the second insulation layer 69. Also,the second insulation layers 69 are used as an insulation layer betweenthe control gate electrodes of the memory cells and include an oxidelayer, such as a silicon oxide layer. The second sacrificial layers 68and the second insulation layers 69 are repetitively formed according tothe number of the memory cells desired to be stacked. Although anynumber of memory cells may be stacked, for convenience of explanation,the memory strings each include three stacked memory cells, andtherefore, the memory cell string includes six memory cells.

Referring to FIG. 7E, the insulation layer stack 300 is etched to formcell channel holes 70 exposing two separate portions of the surface ofthe first sacrificial pattern 67A. The cell channel holes 70 are formedto pass through the insulation layer stack 301. As a result of formingthe cell channel holes 70, an insulation layer stack 301 has a structurein which second sacrificial patterns 68A and second insulation patterns69A are alternately stacked. The cell channel holes 70 pass through thesecond sacrificial patterns 68A and the second insulation patterns 69A.Meanwhile, a lower end of the cell channel hole 70 may extend into thefirst sacrificial pattern 67A. However, since the first sacrificialpattern 67A serves as a passivation layer, the cell channel hole 70 doesnot pass through the first pipe gate 63A and stops at the firstsacrificial pattern 67A.

Referring to FIG. 7F, the first sacrificial pattern 67A is removed.Accordingly, the pipe channel hole 65 is again opened.

The first sacrificial pattern 67A may be removed by a wet process, inparticular, a wet strip process. Accordingly, only the first sacrificialpattern 67A may be selectively removed without causing damage to thesecond insulation patterns 69A and the second sacrificial patterns 68A.

Referring to FIG. 7G, a second conductive layer is formed to fill thecell channel hole 70 and planarized using a CMP process or the like. Thesecond conductive layer may include a polysilicon layer, specifically,an undoped polysilicon layer.

Due to such a planarization process, columnar cell channels 71A areformed within the cell channel holes 70, and a first pipe channel 71B isformed within the pipe channel hole 65. The first pipe channel 71Bcouples the bottoms of the adjacent cell channels 71A. Accordingly, thecell channels 71A and the first pipe channel 71B collectively form aU-shaped structure. Because the first pipe channel 71B closes theopening at the bottom of the cell channel holes 70 before the pipechannel hole 65 is filled, the pipe channel hole 65 has a hollow regioninside. That is, when forming the second conductive layer used as thecell channel 71A and the first pipe channel 71B, the second conductivelayer is not formed within the pipe channel hole 65 once the bottom ofthe cell channel hole 70 is clogged. Thus, the hollow region may beformed inside the pipe channel hole 65.

Referring to FIG. 7H, a slit etching process is performed to form a slit72. The slit 72 is formed in the insulation layer stack 301 to form theinsulation layer stack 302 having second sacrificial patterns 68B andsecond insulation patterns 69B, which are alternately stacked. Further,the bottom of the slit 72 extends to the lowermost second sacrificialpattern 68B.

During the slit etching process for forming the slit 72, the etching maybe stopped at the second sacrificial pattern 68B formed of nitride.Consequently, damage to the first pipe channel 71B and the first pipegate 63A may be prevented.

Referring to FIG. 7I, the second sacrificial patterns 68B areselectively removed. Accordingly, undercuts 73 are formed between thesecond insulation patterns 69B where the second sacrificial patterns 68Bare removed.

Referring to FIG. 7J, a charge storage or charge trapping layer 74 isformed on a resulting structure including the undercuts 73. The chargestorage or charge trapping layer 74 may include a blocking layer, acharge trap layer, and a tunnel insulation layer. That is, the chargestorage or charge trapping layer 74 is formed by sequentially stackingthe blocking layer, the charge trap layer, and the tunnel insulationlayer. The blocking layer prevents charges from passing through thecharge trap layer and moving toward the gate electrode. The blockinglayer may include an oxide layer formed by a thermal oxidation processor a deposition process. The tunnel insulation layer may include anoxide layer, such as a silicon oxide layer. The charge trap layer isused as an actual data storage and includes a charge trap layer whichtraps charges in a deep level trap site. The charge trap layer mayinclude a nitride layer. Therefore, the charge storage or chargetrapping layer 74 may have an oxide-nitride-oxide (ONO) structure.

A third conductive layer 75 is formed on the charge storage or chargetrapping layer 74 to fill the undercuts 73. The third conductive layer75 may include a silicon layer. In particular, the third conductivelayer 75 includes a polysilicon layer, specifically, an undopedpolysilicon layer. The third conductive layer 75 is used as a thecontrol gate electrodes of the memory cell.

Referring to FIG. 7K, control gate electrodes 75A are formed byselectively separating the third conductive layer 75. The control gateelectrodes 75A surround the cell channels 71A while filling theundercuts 73. As a result, the cell channels 71A pass through thecontrol gate electrodes 75A, and a charge storage or charge trappinglayer 74A is formed between the cell channels 71A and the control gateelectrodes 75A. In order to form the control gate electrodes 75A, anetch-back process is used. The use of the etch-back process makes iteasy to selectively separate the third conductive layer 75 to form thecontrol gate electrodes 75A. When forming the control gate electrodes75A, the control gate electrode buried in the lowermost undercut 73becomes the second pipe gate 75B.

As such, due to the formation of the control gate electrodes 75A, twomemory strings MS1 and MS2, in which second insulation patterns 69B andcontrol gate electrodes 75A are alternately stacked, are formed.

A second pipe gate 75B is formed under the memory strings MS1 and MS2.The charge storage or charge trapping layer 74A, the pipe gate tunnelinsulation layer 66, and the polishing stop pattern 64 serve as aninsulation layer between the second pipe gate 75B and the first pipegate 63A. The bottoms of the adjacent cell channels 71A are coupledtogether through the first pipe channel 71B. The first pipe channel 71Bis buried within the pipe channel hole 65. The bottoms of the cellchannels 71A, which are surrounded by the second pipe gate 75B, arereferred to as the second pipe channels 71C. The second pipe gate 75Band the second pipe channels 71C form two second pipe channeltransistors PCTr2, and the first pipe gate 63A and the first pipechannel 71B form a first pipe channel transistor PCTr1.

The semiconductor memory device in accordance with the third exemplaryembodiment of the present invention includes the first pipe gate 63A andthe second pipe gate 75B.

FIG. 8 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a fourth exemplaryembodiment of the present invention.

Referring to FIG. 8, the nonvolatile memory device includes a pair ofcell channels 77A protruding from a substrate 61, a first pipe channel77B coupling the bottoms of the pair of the cell channels 77A, a firstpipe gate 63A in which the first pipe channel 77B is buried, a secondpipe gate 80B surrounding the bottoms of the cell channels 77A, andcontrol gate electrodes 80A surrounding the cell channels 77A. Thecontrol gate electrodes 80A between the cell channels 77A are separatedfrom one another by a slit 78. Due to the second pipe gate 80B, thebottoms of the cell channels 77A become second pipe channels 77C.

Specifically, a first insulation layer 62 is formed between thesubstrate 61 and the first pipe gate 63A. The first insulation layer 62may include an oxide layer, such as a silicon oxide layer. The substrate61 may include a silicon substrate. The first pipe gate 63A may includea silicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 77A, the first pipe channel 77B, and the second pipechannels 77C are formed of the same material. For example, the cellchannels 77A, the first pipe channel 77B, and the second pipe channels77C may include a polysilicon layer, specifically, an undopedpolysilicon layer. The cell channels 77A, the first pipe channel 77B,and the second pipe channels 77C collectively form a U-shaped structure.

The cell channels 77A have a columnar structure, and the first pipechannel 77B fills the first pipe gate 63A. The cell channels 77A aresurrounded by the control gate electrodes 80A and second insulationpatterns 69B, which are alternately stacked. The first pipe gate 63A hasa pipe channel hole 65, and a pipe tunnel insulation layer 66 is formedon the surface of the pipe channel hole 65. The control gate electrodes80A fill undercuts 79 formed between the second insulation patterns 69B.A charge storage or charge trapping layer 76 is formed between thecontrol gate electrodes 80A and the cell channels 77A. The chargestorage or charge trapping layer 76 is formed to surround the cellchannel 77A. The charge storage or charge trapping layer 76 includes ablocking layer, a charge trap layer, and a tunnel insulation layer. Thelowermost control gate electrode becomes the second pipe gate 80B.

Two memory strings MS1 and MS2 are formed by the slit 78. A first pipechannel transistor PCTr1 is formed by the first pipe gate 63A and thefirst pipe channel 77B, and two second pipe channel transistors PCTr2are formed by the second pipe gate 80B and the second pipe channels 77C.The two memory strings MS1 and MS2 are coupled to the first and secondpipe channel transistors PCTr1 and PCTr2. The first pipe channeltransistor PCTr1 and the second pipe channel transistor PCTr2 arecoupled in series. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the first and second pipe channel transistorsPCTr1 and PCTr2 to thereby constitute a single memory cell string. Forexample, where three memory cells are formed in each memory string, thesingle memory cell string includes six memory cells.

FIGS. 9A to 9F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with a fourthexemplary embodiment of the present invention. In the fourth exemplaryembodiment, the processes until the process of again opening the pipechannel hole are performed in the same manner as those of the thirdembodiment as illustrated in FIGS. 7A to 7F, and therefore, adescription of such processes is omitted for the fourth exemplaryembodiment.

Referring to FIG. 9A, the pipe channel hole 65 coupling the pair of thepipe channel holes 70 is again opened.

Referring to FIG. 9B, a charge storage or charge trapping layer 76 isformed on an insulation layer stack 301, including the cell channelholes 70 and the pipe channel hole 65. The charge storage or chargetrapping layer 76 may include a blocking layer, a charge trap layer, anda tunnel insulation layer. That is, the charge storage or chargetrapping layer 76 is formed by sequentially stacking the blocking layer,the charge trap layer, and the tunnel insulation layer. The blockinglayer prevents charges from passing through the charge to trap layer andmoving toward the gate electrode. The blocking layer may include anoxide layer formed by a thermal oxidation process or a depositionprocess. The tunnel insulation layer may include an oxide layer, such asa silicon oxide layer. The charge trap layer is used as an actual datastorage and includes a charge trap layer which traps charges in a deeplevel trap site. The charge trap layer may include a nitride layer.Thus, the charge storage or charge trapping layer 76 may have an ONOstructure.

A second conductive layer is formed on the charge storage or chargetrapping layer 76 to fill the cell channel holes 70, and planarizedusing a CMP process or the like. The second conductive layer may includea polysilicon layer, specifically, an undoped polysilicon layer.

Due to such a planarization process, columnar cell channels 77A areformed within the cell channel holes 70, and a first pipe channel 77B isformed within the pipe channel hole 65. The first pipe channel 77Bcouples the pair of the adjacent cell channels 77A. Accordingly, thecell channels 77A and the first pipe channel 77B collectively form aU-shaped structure. Due to the first pipe channel 77B, a hollow regionmay be formed inside of the pipe channel hole 65.

Referring to FIG. 9C, a slit etching process is performed to form a slit78. The slit 78 is formed in the insulation layer stack 301 to form theinsulation layer stack 302 having second sacrificial patterns 68B andsecond insulation patterns 69B, which are alternately stacked. Further,the bottom of the slit 78 extends to the lowermost second sacrificialpattern 68B.

During the slit etching process for forming the slit 78, the etching maybe stopped at the second sacrificial pattern 68B formed of nitride.Consequently, the damage of the first pipe channel 77B and the firstpipe gate 63A is prevented.

Referring to FIG. 9D, the second sacrificial pattern 68B is selectivelyremoved. Accordingly, undercuts 79 are formed between the secondinsulation patterns 69B where the second sacrificial patterns 68B areremoved.

Referring to FIG. 9E, a third conductive layer 80 is formed to fill theundercuts 79. The third conductive layer 80 may include a silicon layer.In particular, the third conductive layer 80 includes a polysiliconlayer, specifically, an undoped polysilicon layer. The third conductivelayer 80 is used as a control gate electrode of the memory cell.

Referring to FIG. 9F, control gate electrodes 80A are formed byselectively separating the third conductive layer 80. The control gateelectrodes 80A surround the cell channels 77A while filling theundercuts 79. As a result, the cell channels 77A pass through thecontrol gate electrodes 80A, and a charge storage or charge trappinglayer 76 is formed between the cell channels 77A and the control gateelectrodes 80A. In order to form the control gate electrodes 80A, anetch-back process is used. The use of the etch-back process makes iteasy to selectively separate the third conductive layer 80 to form thecontrol gate electrodes 80A. When forming the control gate electrodes80A, the control gate electrode buried in the lowermost undercut 79becomes the second pipe gate 80B.

As such, due to the formation of the control gate electrodes 80A, twomemory strings MS1 and MS2, in which second insulation patterns 69B andcontrol gate electrodes 80A are alternately stacked, are formed.

A second pipe gate 80B is formed under the memory strings MS1 and MS2.The pipe gate tunnel insulation layer 66 and the polishing stop pattern64 serve as an insulation layer between the second pipe gate 80B and thefirst pipe gate 63A. The bottoms the adjacent cell channels 77A arecoupled together through the first pipe channel 77B. The first pipechannel 77B is buried within the pipe channel hole 65. The bottoms ofthe cell channels 77A, which are surrounded by the second pipe gate 80B,are referred to as the second pipe channels 77C. The second pipe gateBOB and the second pipe channels 77C form two second pipe channeltransistors PCTr2, and the first pipe gate 63A and the first pipechannel 77B form a first pipe channel transistor PCTr1.

The semiconductor memory device in accordance with the fourth exemplaryembodiment of the present invention includes the first pipe gate 63A andthe second pipe gate 80B.

FIG. 10 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a fifth exemplaryembodiment of the present invention.

Referring to FIG. 10, the nonvolatile memory device includes a pair ofcell channels 90A protruding from a substrate 81, a pipe channel 90Bcoupling the bottoms of the pair of the cell channels 90A, a pipe gate85A surrounding the bottoms of the cell channels 90A, first and secondinsulation layers 82 and 84 in which the pipe channel 90B is buried, andcontrol gate electrodes 94A surrounding the cell channels 90A. Thecontrol gate electrodes 94A between the cell channels 90A are separatedfrom one another by a slit 92. Due to the pipe gate 85A, the bottoms ofthe cell channels 90A become a pipe channel 90B.

Specifically, the substrate 81 may include a silicon substrate. Thefirst insulation layer 82 and the second insulation later 84 may includean oxide layer, such as a silicon oxide layer. The first insulationlayer 82 and the second insulation layer 84 have a pipe channel hole83A. Hereinafter, the first insulation layer 82 and the secondinsulation layer 84 together may be referred to as a pipe insulationlayer.

The pipe gate 85A formed on the second insulation layer 84 may include asilicon layer, in particular, an N′ polysilicon layer.

The cell channels 90A and the pipe channel 90B are formed of the samematerial. For example, the cell channels 90A and the pipe channel 90Bmay include a polysilicon layer, specifically, an undoped polysiliconlayer. The cell channels 90A and the pipe channel 90B collectively forma U-shaped structure.

The cell channels 90A are surrounded by the control gate electrodes 94Aand the third insulation patterns 86B, which are alternately stacked.Sidewalls of the cell channel 90A are surrounded by a charge storage orcharge trapping layer 89, and the inside of the cell channels 90A isfilled with a fourth insulation pattern 91. The charge storage or chargetrapping layer 89 may include a blocking layer, a charge trap layer, anda tunnel insulation layer. The fourth insulation pattern 91 may includean oxide layer, such as a silicon oxide layer.

The pipe gate 85A is formed under the lowermost control gate electrode94A, and the pipe gate 85A serves as an etch stop layer during theformation of the slit 92. A silicide layer 95 is formed on portions ofthe surface of the pipe gate 85A that are exposed by the slit 92.

Two memory strings MS1 and MS2 are formed by the slit 92. A pipe channeltransistor PCTr is formed by the pipe gate 85A and the pipe channel 90B.The two memory strings MS1 and MS2 are coupled to the pipe channeltransistor PCTr. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the pipe channel transistor PCTr to therebyconstitute a single memory cell string. For example, where three memorycells are formed in each memory string, the single memory cell stringincludes six memory cells.

In the fifth exemplary embodiment, the pipe gate 85A is formed under thelowermost control gate electrode 94A, and the single pipe channeltransistor having the pipe gate 85A is provided. Since the pipe gate 85Aserves as an etch stop layer during the formation of the slit 92, damageto the pipe channel 90B buried in the pipe channel hole 83A may beprevented.

FIGS. 11A to 11I are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the fifthexemplary embodiment of the present invention.

Referring to FIG. 11A, a first insulation layer 82 is formed on asubstrate 81. The substrate 81 may include a silicon substrate. Thefirst insulation layer 82 may include an oxide layer.

A first sacrificial layer 83 is formed on the first insulation layer 82.The first sacrificial layer 83 may be formed by a photolithographyprocess and an etching process. The first sacrificial layer 83 mayinclude amorphous silicon or silicon germanium compound.

A second insulation layer 84 is formed on the first sacrificial layer 83and planarized until the surface of the first sacrificial layer 83 isexposed. The planarization process may include a CMP process.

Referring to FIG. 11B, a first conductive layer 85 is formed on aresulting structure, including the first sacrificial layer 83 and thesecond insulation layer 84. The first conductive layer 85 may include asilicon layer, in particular, an N⁺ polysilicon layer. The firstconductive layer 85 is used as a pipe gate.

An insulation layer stack 400, in which third insulation layers 86 andsecond sacrificial layers 87 are alternately stacked, is formed on thefirst conductive layer 85. The second sacrificial layers 87 may includea nitride layer, such as a silicon nitride layer. The uppermost layer ofthe insulation layer stack 400 is the third insulation layer 86. Also,the third insulation layers 86 are used as an insulation layer betweenthe control gate electrodes of the memory cells and may include an oxidelayer, such as a silicon oxide layer. The second sacrificial layers 87and the third insulation layers 86 are repetitively formed according tothe number of the memory cells desired to be stacked. Although anynumber of memory cells may be stacked, for convenience of explanation,with regards to the fifth exemplary embodiment of the present invention,the memory strings each include three stacked memory cells, andtherefore, the memory cell string includes six memory cells.

Referring to FIG. 11C, the insulation layer stack 400 and the firstconductive layer 85 are etched to form cell channel holes 88 exposingtwo separate portions of the surface of the first sacrificial layer 83.The cell channel holes 88 are formed to pass through the insulationlayer stack 400 and the first conductive layer 85. As a result offorming the cell channel holes 88, an insulation layer stack 401 havinga structure in which third insulation patterns 86A and secondsacrificial patterns 87A are alternately stacked and a pipe gate 85A areformed. The cell channel holes 88 pass through the second sacrificialpatterns 87A and the third insulation patterns 86A.

Referring to FIG. 11D, the first sacrificial layer 83 is removed.Accordingly, the pipe channel hole 83A is again opened.

The first sacrificial layer 83 may be removed by a wet process, inparticular, a wet strip process. Accordingly, only the first sacrificiallayer 83 may be selectively removed without causing damage to the thirdinsulation patterns 86A and the second sacrificial patterns 87A.

Referring to FIG. 11E, a charge storage or charge trapping layer 89 isformed over the insulation layer stack 401, including the cell channelholes 88 and the pipe channel hole 83A. The charge storage or chargetrapping layer 89 may include a blocking layer, a charge trap layer, anda tunnel insulation layer. That is, the charge storage or chargetrapping layer 89 may be formed by sequentially stacking the blockinglayer, the charge trap layer, and the tunnel insulation layer. Theblocking layer prevents charges from passing through the charge traplayer and moving toward the gate electrode. The blocking layer mayinclude an oxide layer formed by a thermal oxidation process or adeposition process. The tunnel insulation layer may include an oxidelayer, such as a silicon oxide layer. The charge trap layer is used asan actual data storage and includes a charge trap layer which trapscharges in a deep level trap site. The charge trap layer may include anitride layer. Therefore, the charge storage or charge trapping layer 89may have an oxide-nitride-oxide (ONO) structure.

A second conductive layer and a fourth insulation layer 91 are formed onthe charge storage or charge trapping layer 89 to fill the cell channelholes 88 and are planarized using a CMP process or the like. The secondconductive layer may include a polysilicon layer, specifically, anundoped polysilicon layer.

Due to such a planarization process, the second conductive layer becomescolumnar cell channels 90A, which are formed within the cell channelholes 88, and a pipe channel 90B, which is formed within the pipechannel hole 83A. That is, the cell channels 90A and the pipe channel90B are formed from the second conductive layer. The pipe channel 90Bcouples the pair of the adjacent cell channels 90A. Accordingly, thecell channels 90A and the pipe channel 90B collectively form a U-shapedstructure. Due to the pipe channel 90B, a hollow region is formed insidethe pipe channel hole 83A. Further, in this exemplary embodiment, thebottom of the cell channel 90A, that is, the portion surrounded by thepipe gate 85A, is considered part of the pipe channel 90B.

Referring to FIG. 11F, a slit etching process is performed to form aslit 92. The slit 92 is formed in the insulation layer stack 402, andthe bottom of the slit 92 extends to the pipe gate 85A. The insulationlayer stack 402 has a structure in which the third insulation patterns86B and the sacrificial patterns 87B are alternately stacked.

During the slit etching process for forming the slit 92, the etching maybe stopped at the pipe gate 85A. Consequently, damage to the pipechannel 90B is prevented.

Referring to FIG. 11G, the second sacrificial patterns 87B areselectively removed. Accordingly, undercuts 93 are formed between thethird insulation patterns 86B where the second sacrificial patterns 87Bare removed.

Referring to FIG. 11H, a third conductive layer 94 is formed to fill theundercuts 93. The third conductive layer 94 may include a polysiliconlayer or a metal layer. The metal layer may include titanium. The thirdconductive layer 94 is used as the control gate electrode of the memorycell.

Referring to FIG. 11I, when the third conductive layer 94 includes ametal layer, a silicide process is performed to form a silicide 95 onthe surface of the pipe gate 85A. The silicide 95 may include titaniumsilicide.

Control gate electrodes 94A are formed by selectively separating thethird conductive layer 94. The control gate electrodes 94A surround thecell channel 90A while filling the undercuts 93. As a result, the cellchannels 90A pass through the control gate electrodes 94A, and a chargestorage or charge trapping layer 89 is formed between the cell channels90A and the control gate electrodes 94A. In order to form the controlgate electrodes 94A, an etch-back process is used. The use of theetch-back process makes it easy to separate the control gate electrodes94A.

As such, due to the formation of the control gate electrodes 94A, twomemory strings MS1 and MS2, in which third insulation patterns 86B andcontrol gate electrodes 94A are alternately stacked, are formed.

A pipe gate 85A is formed under the memory strings MS1 and MS2, and asecond insulation layer 84 is formed under the pipe gate 85A. Thebottoms of the pair of the adjacent cell channels 90A are coupledtogether through the pipe channel 90B. The pipe channel 90B is buriedwithin the pipe channel hole 83A. The bottom of the cell channel 90Asurrounded by the pipe gate 85A is considered to be part of the pipechannel 90B. The pipe gate 85A and the pipe channel 90B form a pipechannel transistor.

FIG. 11J illustrates a modification of the fifth exemplary embodiment.When the third conductive layer 94 includes a polysilicon layer, a metallayer deposition and a silicide (95) process may be performed after theformation of the control gate electrodes 94A. Accordingly, the silicide95 may also be formed at the sidewalls of the control gate electrodes94A. The metal layer is removed after the silicide (95) process.

FIG. 12 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a sixth exemplaryembodiment of the present invention.

Referring to FIG. 12, the nonvolatile memory device includes a pair ofcell channels 96A protruding from a substrate 81, a pipe channel 96Bcoupling the bottoms of the pair of the cell channels 96A, a pipe gate85A surrounding the bottoms of the cell channels 96A, first and secondinsulation layers 82 and 84 in which the pipe channel 96B is buried, andcontrol gate electrodes 101A surrounding the cell channels 96A. Thecontrol gate electrodes 101A between the cell channels 96A are separatedfrom one another by a slit 98. Due to the pipe gate 85A, the bottoms ofthe cell channels 96A become a pipe channel 96B.

Specifically, the substrate 81 may include a silicon substrate. Thefirst insulation layer 82 and the second insulation later 84 may includean oxide layer, such as a silicon oxide layer. The first insulationlayer 82 and the second insulation layer 84 have a pipe channel hole83A. Hereinafter, with regards to the sixth exemplary embodiment, thefirst insulation layer 82 and the second insulation layer 84 togetherwill be referred to as a pipe insulation layer.

The pipe gate 85A formed on the second insulation layer 84 may include asilicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 96A and the pipe channel 96B are formed of the samematerial. For example, the cell channels 96A and the pipe channel 96Bmay include a polysilicon layer, specifically, an undoped polysiliconlayer. The cell channels 96A and the pipe channel 96B collectively forma U-shaped structure.

The cell channels 96A are surrounded by the control gate electrodes 101Aand the third insulation patterns 86B, which are alternately stacked.Sidewalls of the cell channel 96A are surrounded by a charge storage orcharge trapping layer 100A, and the inside of the cell channels 96A isfilled with the fourth insulation pattern 97. The charge storage orcharge trapping layer 100A may include a blocking layer, a charge traplayer, and a tunnel insulation layer. The fourth insulation pattern 97may include an oxide layer, such as a silicon oxide layer.

The pipe gate 85A is formed under the lowermost control gate electrode101A, and the pipe gate 85A serves as an etch stop layer during theformation of the slit 98.

Two memory strings MS1 and MS2 are formed by the slit 98. A pipe channeltransistor PCTr is formed by the pipe gate 85A and the pipe channel 96B.The two memory strings MS1 and MS2 are coupled to the pipe channeltransistor PCTr. Consequently, the two memory strings MS1 and MS2 arecoupled in series through the pipe channel transistor PCTr to therebyconstitute a single memory cell string. For example, where three memorycells are formed in each memory string, the single memory cell stringincludes six memory cells.

In the sixth exemplary embodiment, the pipe gate 85A having a flat shapeis formed under the lowermost control gate electrode 101A, and thesingle pipe channel transistor having the pipe gate 85A is provided.Since the pipe gate 85A serves as an etch stop layer during theformation of the slit 98, damage to the pipe channel 96B buried in thepipe channel hole 83A may be prevented.

FIGS. 13A to 13F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with a sixthexemplary embodiment of the present invention. In the sixth exemplaryembodiment, the processes until the process of opening the pipe channelhole 83A are performed in the same manner as those of the fifthexemplary embodiment as illustrated in FIGS. 11A to 11D.

Referring to FIG. 13A, the pipe channel hole 83A coupling the pair ofthe pipe channel holes 88 is opened.

Referring to FIG. 13B, a second conductive layer and a fourth insulationlayer 97 are formed to fill the cell channel holes 88 and planarizedusing a CMP process or the like. The second conductive layer may includea polysilicon layer, specifically, an undoped polysilicon layer.

Due to such a planarization process, columnar cell channels 96A areformed within the cell channel holes 88, and a pipe channel 96B isformed within the pipe channel hole 83A. The cell channels 96A and thepipe channel 96B are formed by the second conductive layer. The pipechannel 96B couples the pair of the adjacent cell channels 96A.Accordingly, the cell channel 96A and the pipe channel 96B collectivelyform a U-shaped structure. Due to the fourth insulation layer 97, ahollow region may be formed inside the pipe channel hole 83A.

Referring to FIG. 13C, a slit etching process is performed to form aslit 98. The slit 98 is formed in the insulation layer stack 401 to formthe insulation layer stack 402 having third insulation patterns 86B andsecond sacrificial patterns 87B, which are alternately stacked. Further,the bottom of the slit 98 extends to the pipe gate 85A.

During the slit etching process for forming the slit 98, the etching maybe stopped at the pipe gate 85A. Consequently, damage to the pipechannel 96B may be prevented.

Referring to FIG. 13D, the second sacrificial patterns 87B areselectively removed. Accordingly, undercuts 99 are formed between thethird insulation patterns 86B where the second sacrificial patterns 87Bare removed.

Referring to FIG. 13E, a charge storage or charge trapping layer 100 isformed on a resulting structure including the undercuts 99. The chargestorage or charge trapping layer 100 may include a blocking layer, acharge trap layer, and a tunnel insulation layer. That is, the chargestorage or charge trapping layer 100 is formed by sequentially stackingthe blocking layer, the charge trap layer, and the tunnel insulationlayer. The blocking layer prevents charges from passing through thecharge trap layer and moving toward the gate electrode. The blockinglayer may include an oxide layer formed by a thermal oxidation processor a deposition process. The tunnel insulation layer may include anoxide layer, such as a silicon oxide layer. The charge trap layer isused as an actual data storage and includes a charge trap layer whichtraps charges in a deep level trap site. The charge trap layer mayinclude a nitride layer. Therefore, the charge storage or chargetrapping layer 100 may have an oxide-nitride-oxide (ONO) structure.

A third conductive layer 101 is formed on the charge storage or chargetrapping layer 100 to fill the undercuts 101. The third conductive layer101 may include a silicon layer or a metal layer. The third conductivelayer 101 is used as the control gate electrodes of the memory cell.

Referring to FIG. 13F, control gate electrodes 101A are formed byselectively separating the third conductive layer 101. The control gateelectrodes 101A surround the cell channel 96A while filling theundercuts 99. As a result, the cell channels 96A pass through thecontrol gate electrodes 101A, and a charge storage or charge trappinglayer 100A is formed between the cell channels 96A and the control gateelectrodes 101A. In order to form the control gate electrodes 101A, aCMP process and an etch-back process are sequentially performed. The useof the etch-back process makes it easy to selectively separate the thirdconductive layer 101 to form the control gate electrodes 101A.

As such, due to the formation of the control gate electrodes 101A, twomemory strings MS1 and MS2, in which third insulation patterns 86B andcontrol gate electrodes 101A are alternately stacked, are formed.

A pipe gate 85B is formed under the memory strings MS1 and MS2, and asecond insulation layer 84 is formed under the pipe gate 85A. Thebottoms of the adjacent cell channels 96A are coupled together throughthe pipe channel 96B. The pipe channel 96B is buried within the pipechannel hole 83A. The bottoms of the cell channels 96A, which aresurrounded by the pipe gate 85A, are considered to be part of the pipechannel 96B. The pipe gate 85A and the pipe channel 96B form a pipechannel transistor.

FIG. 14 is a cross-sectional view illustrating a structure of anonvolatile memory device in accordance with a seventh exemplaryembodiment of the present invention.

Referring to FIG. 14, the nonvolatile memory device includes a pair ofcell channels 119A protruding from a substrate 110, a pipe channel 119Bcoupling the bottoms of the pair of the cell channels 119A, a pipe gate114A surrounding the bottoms of the cell channels 119A, first and secondinsulation layers 111 and 113 in which the pipe channel 119B is buried,and control gate electrodes 116B surrounding the cell channels 119A. Thecontrol gate electrodes 116B between the cell channels 119A areseparated from one another by a slit 121.

Specifically, the substrate 110 may include a silicon substrate. Thefirst insulation layer 111 and the second insulation later 113 mayinclude an oxide layer, such as a silicon oxide layer. The firstinsulation layer 111 and the second insulation layer 113 have a pipechannel hole 112A. Hereinafter, in the seventh exemplary embodiment, thefirst insulation layer 111 and the second insulation layer 113 togetherwill be referred to as a pipe insulation layer.

The pipe gate 114A formed on the second insulation layer 113 includes asilicon layer, in particular, an N⁺ polysilicon layer.

The cell channels 119A and the pipe channel 119B are formed of the samematerial. For example, the cell channels 119A and the pipe channel 119Binclude a polysilicon layer, specifically, an undoped polysilicon layer.The cell channels 119A and the pipe channel 119B collectively form aU-shaped structure.

The cell channels 119A are surrounded by the control gate electrodes116B and the third insulation patterns 115B, which are alternatelystacked. Sidewalls of the cell channel 119A are surrounded by a chargestorage or charge trapping layer 118, and the inside of the cellchannels 119A is filled with a fourth insulation pattern 120. The chargestorage or charge trapping layer 118 may include a blocking layer, acharge trap layer, and a tunnel insulation layer. The fourth insulationpattern 120 may include an oxide layer, such as a silicon oxide layer.

The pipe gate 114A is formed under the lowermost control gate electrode116B, and the pipe gate 114A serves as an etch stop layer during theformation of the slit 121.

Two memory strings MS1 and MS2 are formed by the slit 121. A pipechannel transistor PCTr is formed by the pipe gate 114A and the pipechannel 119B. The two memory strings MS1 and MS2 are coupled to the pipechannel transistor PCTr. Consequently, the two memory strings MS1 andMS2 are coupled in series through the pipe channel transistor PCTr tothereby constitute a single memory cell string. For example, where threememory cells are formed in each memory string, the single memory cellstring includes six memory cells.

In the seventh exemplary embodiment, the pipe gate 114A is formed underthe lowermost control gate electrode 116B, and the single pipe channeltransistor having the pipe gate 114A is provided. Since the pipe gate114A serves as an etch stop layer during the formation of the slit 121,damage to the pipe channel 119B buried in the pipe channel hole 112A maybe prevented.

FIGS. 15A to 15F are cross-sectional views illustrating a method forfabricating a nonvolatile memory device in accordance with the seventhexemplary embodiment of the present invention.

Referring to FIG. 15A, a first insulation layer 111 is formed on asubstrate 110. The substrate 110 may include a silicon substrate. Thefirst insulation layer 111 may include an oxide layer.

A sacrificial layer 112 is formed on the first insulation layer 111. Thesacrificial layer 112 may be formed by a photolithography process and anetching process. The sacrificial layer 112 may include a nitride layer,such as a silicon nitride layer.

A second insulation layer 113 is formed on the sacrificial layer 112 andplanarized until the surface of the sacrificial layer 112 is exposed.The planarization process may include a CMP process. The secondinsulation layer 113 may include an oxide layer.

Referring to FIG. 15B, a first conductive layer 114 is formed on aresulting structure including the sacrificial layer 112 and the secondinsulation layer 113. The first conductive layer 114 may include asilicon layer, in particular, an N⁺ polysilicon layer. The firstconductive layer 114 is used as a pipe gate.

A cell stack 500, in which third insulation layers 115 and secondconductive layers 116 are alternately stacked, is formed on the firstconductive layer 114. The third insulation layers 115 separate thecontrol gate electrodes of the plurality of memory cells stacked in avertical direction. The third insulation layers 115 may include an oxidelayer. The uppermost layer of the cell stack 500 is one of the thirdinsulation layers 115. Also, the second conductive layers 116 are usedas control gate electrodes of a memory cell. The second conductivelayers 116 include a polysilicon layer doped with a P-type impurity orN-type impurity. In this exemplary embodiment, the second conductivelayers 116 are formed of P⁺ polysilicon. The third insulation layers 115and the second conductive layers 116 are repetitively formed accordingto the number of the memory cells desired to be stacked. Although anynumber of memory cells may be stacked, for convenience of explanation,the memory strings each include three stacked memory cells, andtherefore, the memory cell string includes six memory cells. A thirdconductive layer for a selection transistor may be further stacked, andits illustration is omitted.

Referring to FIG. 15C, the cell stack 500 and the first conductive layer114 are etched to form cell channel holes 117 exposing two separateportions of the surface of the sacrificial pattern 112. The cell channelholes 117 are formed to pass through the cell stack 500 and the firstconductive layer 114. As a result of forming the cell channel holes 117,the cell stack 501 has a structure in which third insulation patterns115A and second conductive patterns 116A are alternately stacked. Also,the first conductive layer becomes the pipe gate 114A. The cell channelholes 117 pass through the third insulation patterns 115A, the secondconductive patterns 116A, and the pipe gate 114A. Before forming thecell channel holes 117, the ends of the second conductive patterns 115Amay be etched, using, for example, a sliming etching process, to form astepped shape structure.

Referring to FIG. 15D, the sacrificial layer 112 is removed.Accordingly, the pipe channel hole 112A is opened. The sacrificial layer112 may be removed by a wet process, in particular, a wet strip process.Accordingly, only the sacrificial layer 112 may be selectively removedwithout causing damage to the pipe gate 114A, the second conductivepatterns 116A, and the third insulation patterns 115A.

An opening exists between the pipe channel hole 112A and the adjacentcell channel holes 117. Accordingly, the cell channel holes 117 and thepipe channel hole 112A collectively form a U-shaped opening.

Referring to FIG. 15E, a charge storage or charge trapping layer 118, athird conductive layer, and a fourth insulation layer 120 aresequentially formed on a resulting structure including the pipe channelhole 112A. A planarization process is performed to expose the uppermostthird insulation pattern 115A of the cell stack 501. The planarizationprocess may include a CMP process.

Due to such a planarization process, columnar cell channels 119A areformed within the cell channel hole 117, and a pipe channel 119B isformed within the pipe channel hole 112A. The cell channel 119A and thepipe channel 119B are formed by planarizing the third conductive layer.The pipe channel 119B couples the adjacent cell channels 119A.Accordingly, the cell channels 119A and the pipe channel 119Bcollectively form a U-shaped structure. Due to the fourth insulationpattern 120, a hollow region is formed inside of the pipe channel hole112A. Hereinafter, in the seventh exemplary embodiment, the bottomportions of the cell channels 119A surrounded by the pipe gate 114A areconsidered to be part of the pipe channel 119B.

The charge storage or charge trapping layer 118 may include a blockinglayer, a charge trap layer, and a tunnel insulation layer. That is, thecharge storage or charge trapping layer 118 is formed by sequentiallystacking the blocking layer, the charge trap layer, and the tunnelinsulation layer. The blocking layer prevents charges from passingthrough the charge trap layer and moving toward the gate electrode. Theblocking layer may include an oxide layer formed by a thermal oxidationprocess or a deposition process. The tunnel insulation layer includes anoxide layer such as a silicon oxide layer. The charge trap layer is usedas an actual data storage and includes a charge trap layer which trapscharges in a deep level trap site. The charge trap layer may include anitride layer. Therefore, the charge storage or charge trapping layer118 may have an oxide-nitride-oxide (ONO) structure.

The third conductive layer which becomes the cell channels 119A and thepipe channel 119B may include a silicon layer. In particular, the thirdconductive layer may include a polysilicon layer, specifically, anundoped polysilicon layer.

The fourth insulation layer 120 may include an oxide layer. When formingthe fourth insulation layer 120, the bottom of the cell channel holes117 is sealed. Accordingly, a hollow region is formed within the pipechannel hole 112A.

Referring to FIG. 15F, a slit etching process is performed to separatethe control gate electrodes 116B between the adjacent memory strings MS1and MS2. As a result, a slit 121 is formed. In order to form the slit121, the third insulation patterns 115A and the second conductivepatterns 116A are etched, and the etching is stopped at the pipe gate114A. A portion of the pipe gate 114A may be etched as well. However,the slit 121 does not pass through the pipe channel 119B.

As such, due to the formation of the slit 121, two memory strings MS1and MS2, in which third insulation patterns 115B and control gateelectrodes 116B are alternately stacked, are formed. The memory stringsMS1 and MS2 include the charge storage or charge trapping layers 118 andthe cell channels 119A buried in the cell channel holes 117. A fourthinsulation layer 120 is formed within the cell channels 119A. The fourthinsulation layer 120 also forms a hollow region in the pipe channel hole112A.

A pipe gate 114A is formed between the memory strings MS1 and MS2. Thebottoms of the cell channels 119A are coupled together through the pipechannel 119B. The pipe channel 119B is buried in the pipe channel hole112A. The pipe gate 114A and the pipe channel 119B form a pipe channeltransistor.

Due to the pipe gate 114A, damage to the pipe channel 119B is preventedduring the slit etching process.

A silicide (not shown) may be formed on sidewalls of the control gateelectrodes 116B exposed within the slit 121.

In the above-described exemplary embodiments of the present invention,since the etching may be stopped by the passivation layer and the secondpipe gate during the slit etching process, it is possible to preventdamage to the first pipe gate and the pipe channel coupling the columnarcell channels, thereby improving the etching margin.

Furthermore, since the pipe gate is additionally formed under the memorystrings, an increase in the channel distance is prevented, and thus, thelowering of the cell on current may be prevented.

Moreover, since the single pipe gate surrounding the bottoms of the cellchannels is formed, the etching may be stopped at the pipe gate duringthe slit etching process, thereby improving the etching margin andpreventing the lowering of the cell on current.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1-13. (canceled)
 14. A method for fabricating a nonvolatile memorydevice, the method comprising: forming a pipe insulation layer in whicha sacrificial layer is buried; forming a pipe gate over the pipeinsulation layer; forming a cell stack having a pair of cell channelholes; removing the sacrificial layer to form a pipe channel hole;forming a pair of columnar cell channels and a pipe channel by partiallyfilling the cell channel holes and the pipe channel hole; and forming aslit which separates the cell stack into cell strings.
 15. The method ofclaim 14, wherein the forming of the slit comprises etching the cellstack so that the etching is stopped at the pipe gate.
 16. The method ofclaim 14, wherein the forming the cell stack comprises: alternatelystacking a plurality of interlayer insulation layers and a plurality ofgate electrodes over the pipe gate; and etching the plurality ofinterlayer insulation layers and the plurality of gate electrodes toform the cell channel holes.
 17. The method of claim 16, furthercomprising: forming a charge storage or charge trapping layersurrounding sidewalls of the cell channel holes and the pipe channelhole before forming the pair of columnar cell channels and the pipechannel.
 18. The method of claim 16, wherein the forming the slitcomprises etching the cell stack so that the etching is stopped at oneof the lowermost interlayer insulation layer and the pipe gate.
 19. Themethod of claim 14, wherein the forming the cell stack comprises:alternately stacking a plurality of interlayer insulation layers and aplurality of interlayer sacrificial layers over the pipe gate; andetching the plurality of interlayer insulation layers and the pluralityof interlayer sacrificial layers to form the cell channel holes.
 20. Themethod of claim 19, further comprising: removing the interlayersacrificial layers to form undercuts after forming the slit; forming thecharge storage or charge trapping layer covering the undercuts; andfilling the undercuts with a conductive layer to form a plurality ofgate electrodes.
 21. The method of claim 19, wherein the forming of theslit comprises etching the cell stack so that the etching is stopped atone of the lowermost interlayer insulation layer and the pipe gate. 22.The method of claim 14, wherein the sacrificial layer comprises anitride layer, and the pipe insulation layer comprises an oxide layer.23. The method of claim 19, wherein the interlayer sacrificial layercomprises an amorphous carbon or a silicon germanium compound, and theinterlayer insulation layer comprises an oxide layer.
 24. A method forfabricating a nonvolatile memory device, the method comprising: forminga first pipe gate in which a sacrificial layer is buried; forming asecond pipe gate and a cell stack having a pair of cell channel holes;removing the sacrificial layer to form a pipe channel hole; forming apair of columnar cell channels and a pipe channel by partially fillingthe cell channel holes and the pipe channel hole; and forming a slitwhich separates the cell stack into cell strings.
 25. The method ofclaim 24, further comprising: forming a passivation layer disposedbetween the first pipe gate and the second pipe gate.
 26. The method ofclaim 25, wherein the forming the slit comprises etching the cell stackso that the etching is stopped at one of the passivation layer and thesecond pipe gate.
 27. The method of claim 25, wherein the passivationlayer comprises a nitride layer or an oxide layer.
 28. The method ofclaim 24, wherein the forming the second pipe gate and the cell stackcomprises: forming the second pipe gate over the first pipe gate;alternately stacking a plurality of interlayer insulation layers and aplurality of gate electrodes over the second pipe gate; and etching theplurality of interlayer insulation layers and the plurality of gateelectrodes to form the cell channel holes.
 29. The method of claim 28,wherein the forming the slit comprises etching the cell stack so thatthe etching is stopped at one of the lowermost interlayer insulationlayer and the second pipe gate.
 30. The method of claim 25, wherein theforming the second pipe gate and the cell stack comprises: forming thesecond pipe gate over the passivation layer; alternately stacking aplurality of interlayer insulation layers and a plurality of gateelectrodes over the second pipe gate; and etching the plurality ofinterlayer insulation layers and the plurality of gate electrodes toform the cell channel holes.
 31. The method of claim 30, wherein theforming the slit comprises etching the cell stack so that the etching isstopped at one of the lowermost interlayer insulation layer, the secondpipe gate and the passivation layer.
 32. The method of claim 24, furthercomprising: forming a charge storage or charge trapping layersurrounding sidewalls of the cell channel holes and the pipe channelhole before forming the pair of columnar cell channels and the pipechannel.
 33. The method of claim 24, wherein the forming the second pipegate and the cell stack comprises; alternately stacking a plurality ofinterlayer insulation layers and a plurality of interlayer sacrificiallayers over the first pipe gate; and etching the plurality of interlayerinsulation layers and the plurality of interlayer sacrificial layers toform the cell channel holes.
 34. The method of claim 33, furthercomprising: removing the interlayer sacrificial layers to form undercutsafter forming the slit; forming the charge storage or charge trappinglayer covering the undercuts; and filling the undercuts with aconductive layer to form the second pipe gate and a plurality of gateelectrodes.
 35. The method of claim 34, wherein the forming the slitcomprises etching the cell stack so that the etching is stopped at thelowermost interlayer insulation layer.
 36. The method of claim 25,wherein the forming the second pipe gate and the cell stack comprises;alternately stacking a plurality of interlayer insulation layers and aplurality of interlayer sacrificial layers over the passivation layer;and etching the plurality of interlayer insulation layers and theplurality of interlayer sacrificial layers to form the cell channelholes.
 37. The method of claim 36, wherein the forming the slitcomprises etching the cell stack so that the etching is stopped at oneof the lowermost interlayer insulation layer and the passivation layer.38. The method of claim 34, further comprising: forming a metalinterconnection which commonly couples the first pipe gate and thesecond pipe gate.
 39. The method of claim 33, wherein the interlayersacrificial layer comprises a nitride layer, and the interlayerinsulation layer comprises an oxide layer.
 40. The method of claim 33,wherein the sacrificial layer comprises an amorphous carbon or a silicongermanium compound.